A lightweight emulator and assembly compiler (assembler) for the 32-bit SimpleRISC Instruction Set Architecture (ISA), implemented in C.
This project serves as an educational exercise based on Chapters 1–3 of 'Basic Computer Architecture' by Smruti R. Sarangi. The scope and boundaries of this project are strictly limited to these first 3 chapters.
The repository consists of:
- Assembler (
srac.out): A two-pass compiler that tokenizes SimpleRISC assembly files (.asm), builds a label symbol table, resolves branch offsets, and encodes instructions into 32-bit binary words. - Processor Emulator (
processor.out): An emulation engine that simulates the CPU state, including a 1KB memory, register files, and execution loop for the instruction set. - Tests: A lightweight unit testing and functional testing suite verifying assembler parsing and functional execution of algorithms (such as recursive factorial, LCM, and primality testing).
SimpleRISC is an educational RISC ISA introduced in Chapter 3 (Section 3.3.2) of the textbook:
- Registers: 16 general-purpose registers (
r0throughr15), each 32 bits wide.r14is designated as the Stack Pointer (sp) (initialized to the top of memory).r15is designated as the Return Address Register (ra).
- Internal Status Flags: A non-programmer-visible
flagsregister with two fields:flags.E(Equal): Set to 1 if comparison results in equality.flags.GT(Greater Than): Set to 1 if the first operand is greater than the second.
- Instruction Encoding: Every instruction is encoded into a 32-bit value requiring 4 bytes of memory, with multi-byte integers stored in little-endian format.
- Immediate Support: Immediates are supported up to 16 bits (signed, unsigned, or shifted high via modifiers).
- Only the concepts, registers, and instructions introduced in Chapters 1–3 of the book are supported.
- Memory size is limited to 1024 bytes.
- Add 32-bit immediate code generation for other ALU instructions (currently only
movis implemented).