A clean-room, open-source implementation of the system described in:
Bojie Li, Kun Tan, Layong (Larry) Luo, Yanqing Peng, Renqian Luo, Ningyi Xu, Yongqiang Xiong, Peng Cheng, Enhong Chen. "ClickNP: Highly Flexible and High-performance Network Processing with Reconfigurable Hardware." ACM SIGCOMM 2016.
OpenClickNP is a high-level FPGA programming framework for network functions. You write a network application as a graph of communicating elements in a small DSL; OpenClickNP compiles it to AMD/Xilinx Alveo U50 hardware, with optional software, SystemC, and Verilator simulation backends.
This project is a clean-room reimplementation: every line of source is written from the published paper as the only specification. It is licensed under Apache-2.0.
flowchart LR
SRC[".clnp source<br/>(elements + topology)"]
CC["openclicknp-cc<br/>lex → parse → resolve<br/>→ analyses → lower"]
SRC --> CC
CC --> HLS["HLS C++"]
CC --> SC["SystemC"]
CC --> SW["SW emu"]
CC --> VER["Verilator"]
CC --> LINK["v++ link"]
CC --> HOST["XRT host"]
HLS --> VITIS["Vitis HLS"]
VITIS --> VIVADO["Vivado<br/>P&R"]
LINK --> VIVADO
VIVADO --> XCLBIN[".xclbin"]
XCLBIN --> U50["Alveo U50"]
SC --> SCBIN["SystemC sim<br/>(L3, cycle-acc.)"]
SW --> SWBIN["std::thread emu<br/>(L2, fast)"]
VER --> VERBIN["Verilator sim<br/>(L4, RTL)"]
HOST --> HBIN["host program<br/>(libopenclicknp_runtime)"]
HBIN -. XRT .-> U50
classDef src fill:#e8f4f8,stroke:#2b6cb0,color:#1a365d
classDef tool fill:#fef5e7,stroke:#c05621,color:#744210
classDef out fill:#e6fffa,stroke:#2c7a7b,color:#234e52
class SRC,CC src
class HLS,SC,SW,VER,LINK,HOST,VITIS,VIVADO tool
class XCLBIN,U50,SCBIN,SWBIN,VERBIN,HBIN out
The same .clnp source compiles to all six backends without
modification — element bodies are passed through opaquely. See
docs/architecture.md for the full picture.
v0.1. The compiler, runtime, element library (123 elements across 9
categories), and 47 end-to-end applications are in place; all 47 apps
pass place-and-route on the U50 die at 322 MHz with zero CDC violations.
See FINAL_REPORT.md for measured numbers and
PLAN.md for the full design.
New here? Read
docs/getting_started.mdfirst (fresh-install → running example), then write your own element withdocs/first_element.md. Neither needs an FPGA or any AMD/Xilinx tooling.
You do not need an FPGA — or any AMD/Xilinx tools — to build, test, and run OpenClickNP. The compiler, the unit tests (L1), and the software emulator (L2) build from a stock Ubuntu toolchain. Vivado/Vitis, XRT, and a real Alveo U50 are only needed for the synthesis, RTL-sim, and hardware tiers (L3–L5).
For everything except real hardware — compiler, tests, SW emulator:
- Ubuntu 22.04 LTS
- CMake ≥ 3.22
- gcc-11+ or clang-14+
Only for the RTL/hardware tiers (L3/L4/L5):
- AMD Vivado/Vitis 2025.2, XRT ≥ 2.16 (synthesis, link, P&R, real U50)
- Verilator ≥ 5.018, SystemC ≥ 2.3.4 (cycle-accurate / RTL simulation)
git clone https://github.com/bojieli/OpenClickNP.git
cd OpenClickNP
cmake -B build -DCMAKE_BUILD_TYPE=Release
cmake --build build -j
ctest --test-dir buildThis builds openclicknp-cc, the runtime library, and runs the L1 unit
- L2 emulator tests (≈135 tests; the SystemC/Verilator smokes auto-enable when those tools are installed).
./scripts/sim/run_emu.sh examples/PassTraffic./scripts/build/compile.sh examples/PassTraffic --platform u50_xdma
./scripts/build/synth_kernels.sh examples/PassTraffic
./scripts/build/link.sh examples/PassTraffic
./scripts/build/implement.sh examples/PassTrafficOutput: build/PassTraffic/PassTraffic.xclbin.
./scripts/run/program_fpga.sh build/PassTraffic/PassTraffic.xclbin
./scripts/run/run_example.sh examples/PassTrafficcompiler/ — openclicknp-cc, the .clnp DSL → multi-target compiler
runtime/ — libopenclicknp_runtime, host-side library
elements/ — standard element library (123 elements, 9 categories)
shell/ — Vivado/Vitis platform integration for U50 (XDMA + QDMA)
tests/ — L1 unit, L2 emulator, per-element behavioral tests, smokes
examples/ — 47 end-to-end demo applications
eval/ — reproducible HLS / P&R / CDC / throughput / latency runs
scripts/ — build / run / sim / platform-install scripts
docs/ — architecture, compiler internals, language reference
Start here (no FPGA needed):
docs/getting_started.md— fresh install to running example, then on to a real bitstreamdocs/first_element.md— write, compile, and run your own element from scratchdocs/language.md—.clnpDSL reference
Understand the internals:
docs/architecture.md— system layersdocs/compiler_internals.md— compiler walkthroughdocs/verification_levels.md— L1–L5 test pyramid
Design rationale, results, and advanced topics:
PLAN.md— full design plan and roadmapFINAL_REPORT.md— measured results (resources, P&R, CDC)HTTPS_ACCELERATOR.md— advanced, post-v0.1: RSA/AES/SHA crypto elements and OpenSSL ENGINE integration
A per-application README lives in every directory under
examples/; examples/PassTraffic
is the minimal one.
Apache-2.0. See LICENSE.
If you use OpenClickNP in academic work, please cite the original ClickNP paper:
@inproceedings{10.1145/2934872.2934897,
author = {Li, Bojie and Tan, Kun and Luo, Layong (Larry) and Peng, Yanqing and Luo, Renqian and Xu, Ningyi and Xiong, Yongqiang and Cheng, Peng and Chen, Enhong},
title = {ClickNP: Highly Flexible and High Performance Network Processing with Reconfigurable Hardware},
year = {2016},
isbn = {9781450341936},
publisher = {Association for Computing Machinery},
address = {New York, NY, USA},
url = {https://doi.org/10.1145/2934872.2934897},
doi = {10.1145/2934872.2934897},
booktitle = {Proceedings of the 2016 ACM SIGCOMM Conference},
pages = {1--14},
numpages = {14},
keywords = {Reconfigurable Hardware, Network Function Virtualization, FPGA, Compiler},
location = {Florianopolis, Brazil},
series = {SIGCOMM '16}
}