RTL Design & Verification Engineer | VLSI Enthusiast | RISC-V | FPGA | RTL-to-GDSII ASIC Design
I am a hardware engineer obsessed with pushing the boundaries of computer architecture, silicon design, and edge AI. I recently graduated from CUET (B.Sc. ETE, VLSI Major) and am currently building digital systems at ADN Semiconductors and teaching VLSI at MIU.
Whether it's writing Verilog, running physical design scripts, or wiring up a core of RISC-V, I love seeing logic gates come to life.
- EVPIX-RV32 (Custom RISC-V SoC): My flagship project. A 32-bit, 5-stage pipelined RISC-V processor integrated with an IPU and TinyML for real-time edge vision AI.
- Status: Verified via real Basys-3 AMD Artix-7 FPGA prototyping and pushed through a complete RTL-to-GDSII ASIC CMOS layout using the OpenROAD Flow Script.
- Sub-Micron CMOS Research: Published IEEE author on power and propagation delay benchmarking for hardware adders in 90nm technology. Read My Paper in IEEE Xplore Digital Library.
- B.Sc. from CUET: ETE Graduate. Major in Electronics, VLSI (Final Year CGPA: 3.78)
- Secured A+ in all Advanced VLSI Design courses.
- HDLs & Design: Verilog, SystemVerilog
- Architecture: RISC-V, Pipelined CPUs, Custom Accelerators (IPU/TinyML)
- EDA & Physical Design: Vivado,OpenROAD Flow (RTL-to-GDSII), Yosys, KLayout, Cadence Virtuoso
- Simulation & Prototyping: FPGA, Testbench Verification, BIST, UVM, Logisim
